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march 2014 altera corporation ds-1042 datasheet ? 2014 altera corporation. all rights rese rved. altera, arria, cyclone, enpiri on, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera cor poration and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademar ks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current spec ifications in accordance with altera's standard warranty, but reserves the right to make cha nges to any products and services at any time without notice. alt era assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein exce pt as expressly agreed to in writing by altera. altera customers are advised to obtain th e latest version of device specifications before relying on a ny published information and before placing or ders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com subscribe iso 9001:2008 registered enpirion ? power datasheet ER2120QI 2a synchronous buck regulator with integrated mosfets the altera? enpirion? er2120 qi is a synchronous buck controller with internal mosfets packaged in a small 4mmx4mm qfn package. the ER2120QI can support a continuous load of 2a and ha s a very wide input voltage range. with the switching mosfets integrated into the ic, the complete regulator footprint can be very small and provide a much more efficient solution than a linear regulator. the ER2120QI is capable of stand- alone operation or it can be used in a master slave combin ation for multiple outputs that are derived from the same input rail. multiple slave channels (up to six) can be synchroniz ed. this method minimizes the emi and beat frequencies effe ct with multi-c hannel operation. the switching pwm controller dr ives two internal n-channel mosfets in a synchronous-rectified buck converter topology. the synchronous buck converter uses voltage-mode control with fast transient response. the switching regulator provides a maximum static regul ation tolerance of ? 1% over line, load, and temperature ranges. the ou tput is user-adjustable by means of external resistors down to 0.6v. the output is monitored fo r undervoltage events. the switching regulator also has ove rcurrent protection. thermal shutdown is integrated. the ER2120QI features a bi-directional enable pin that allows the part to pull the enable pin low during fault detection. pok delay for ER2120QI is 1ms typical (at 500khz switching frequency). features ? up to 2a continuous output current ? integrated mosfets for small regulator footprint ? adjustable switching fre quency, 500khz to 1.2mhz ? tight output vo ltage regulation, ? 1% over-temperature ? wide input voltage range, 5v ? 10% or 5.5v to 14v ? wide output voltage range, from 0.6v ? simple single-loop voltage- mode pwm control design ? input voltage feed-forward for constant modulator gain ? fast pwm converter transient response ? lossless r ds(on) high side and low side overcurrent protections ? undervoltage detection ? integrated thermal shutdown protection ? power-good indication ? adjustable soft-start ? start-up with pre-bias output ? pb-free (rohs compliant) applications ? fpga power ? point of load applications ? graphics cards ? asic power supplies ? embedded processor and i/o supplies ? dsp supplies figure 1. stand-alone regulator: v in 5.5v to 14v figure 2. stand-alone regulator: v in 4.5v to 5.5v v out + ER2120QI avino agnd sync boot pvin sw pgnd m/s fsw pok en ss fb comp + v in enable power good 5.5v to 14v avin v out + ER2120QI avino agnd sync boot pvin sw pgnd m/s fsw pok en ss fb comp + v in enable power good 4.5v to 5.5v avin 09615 march 14, 2014 rev a
page 2 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation ordering information pin configuration ER2120QI (24 ld qfn) top view *see ?functional pin descri ptions? beginning on page 13 for pin descriptions. part number (note 1) part marking temp. range (c) package (pb-free) pkg. dwg. # ER2120QI (notes 1, 3) 2120 -40 to +85 24 ld 4x4 qfn l24.4x4d evb-ER2120QI evaluation board notes: 1. these altera enpirion pb-free plastic pack aged products employ special pb-free mate rial sets, molding co mpounds/die attach ma terials, and 100% matte tin plate plus anneal (e3 termination finish, wh ich is rohs compliant and co mpatible with both snpb an d pb-free soldering operation s). altera enpirion pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020. 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 pvin sw sw sw sw pgnd pok agnd en sync m/s fsw comp fb ss pgnd pgnd pgnd avin avino boot pvin pvin pvin gnd 25 09615 march 14, 2014 rev a
page 3 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation typical application schematics v out + ER2120QI avino agnd sync boot pvin sw pgnd m/s fsw pok en ss fb comp + v in enable power good 5.5v to 14v avin figure 3. stand-alone regulator: v in 5.5v to 14v v out + ER2120QI avino agnd sync boot pvin sw pgnd m/s fsw pok en ss fb comp + v in enable power good 4.5v to 5.5v avin figure 4. stand-alone regulator: v in 4.5v to 5.5v 09615 march 14, 2014 rev a
page 4 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation ER2120QI with multiple slaved channels ER2120QI en fsw m/s sync avino gnd master slave sw pvin + v out1 v in r t ER2120QI en fsw m/s sync gnd sw pvin + v out2 r t 5k slave ER2120QI en fsw m/s sync gnd sw pvin + v outn r t 5k enable ss 09615 march 14, 2014 rev a
page 5 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation absolute maximum ratings thermal information pvin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +16.5v avin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +6.0v absolute boot voltage, v boot . . . . . . . . . . . . . . . . . . . . . . . . +22.0v upper driver supply voltage, v boot - v sw . . . . . . . . . . . . . . +6.0v all other pins . . . . . . . . . . . . . . . . . . . gnd - 0.3v to avin + 0.3v recommended operating conditions supply voltage on pvin . . . . . . . . . . . . . . . . . . . . . . . . 5.5v to 14v ambient temperature range . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature range . . . . . . . . . . . . . . . . . -40c to +125c thermal resistance ? ja (c/w) ? jc (c/w) qfn package (notes 2, 2) . . . . . . 38 2 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . -65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? caution: do not operate at or near the ma ximum ratings listed for extended periods of time. exposure to su ch conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. ? ja is measured in free air with the compon ent mounted on a high effective thermal condu ctivity test board with ?direct attach? fe atures. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications refer to ?block diagram? and ?typical application schematics?. oper ating conditions unless otherwise noted: v in = 12v, or v av i n = 5v 10%, t a = -40c to +85c. typical are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c parameter symbol test conditions min (note 3) typ max (note 3) unit s v in supply pvin input voltage range v in 5.5 (note 4) 14 (note 5) v v in tied to v av i n 4.5 5.5 v input operating supply current i q v fb = 1.0v 7 ma input standby supply current iq_sby en tied to gnd, v in = 14v 1.25 2 ma series regulator av i n vo l t a g e v av i n o v in > 5.6v 4.5 5.0 5.5 v maximum output current i av i n o v in = 12v 50 ma avin current limit v in = 1 2 v, av i n s h o r t e d t o p g n d 3 0 0 m a power-on reset rising avin por threshold 4.2 4.4 4.49 v falling avin por threshold 3.85 4.0 4.10 v enable rising enable threshold voltage v en_rising 2.7 v falling enable threshold voltage v en_fall 2.3 v enable sinking current i en 500 a oscillator pwm frequency f osc r t = 96k ? 400 500 600 khz r t = 40k ? 960 1200 1440 khz fsw pin tied to avin 800 khz ramp amplitude ? v osc v in = 14v 1.0 v ramp amplitude ? v osc v in = 5v 0.470 v modulator gain v vin /? v osc by design 8 - maximum duty cycle d max f osc = 500khz 88 % maximum duty cycle d max f osc = 1.2mhz 76 % 09615 march 14, 2014 rev a
page 6 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation reference voltage reference voltage v ref 0.600 v system accuracy -1.0 +1.0 % fb pin bias current 80 200 na soft-start soft-start current i ss 20 30 40 a enable soft-start threshold 0.8 1.0 1.2 v enable soft-start threshold hysteresis 12 mv enable soft-start voltage high 2.8 3.2 3.8 v error amplifier dc gain 88 db gain-bandwidth product gbwp 15 mhz maximum output voltage 3.9 4.4 v slew rate sr 5 v/s internal mosfets upper mosfet r ds(on) r ds_upper v av i n = 5v 180 m ? lower mosfet r ds(on) r ds_lower v av i n = 5v 90 m ? pok pok threshold v fb/ v ref rising edge hysteresis 1% 107 111 115 % falling edge hysteresis 1% 86 90 93 % pok rising delay (note 8) t pok_delay f osc = 500khz 1 ms pok leakage current v pok = 5.5v 5 a pok low voltage v pok 0.10 v pok sinking current i pok 0.5 ma protection positive current limit i poc_peak ioc from pvin to sw (notes 6, 7) (t a = 0c to +85c) 2.1 3.5 4.5 a ioc from pvin to sw (notes 6, 7) (t a = -40c to +0c) 2.0 3.4 4.0 a negative current limit i noc_peak ioc from sw to pgnd (notes 6, 7) (t a = 0c to +85c) 2.2 3.0 3.5 a ioc from sw to pgnd (notes 6, 7) (t a =-40c to +85c) 1.9 2.8 3.7 a undervoltage level v fb /v ref 76 80 84 % thermal shutdown setpoint t sd 150 c thermal recovery setpoint t sr 130 c electrical specifications refer to ?block diagram? and ?typical application schematics?. oper ating conditions unless otherwise noted: v in = 12v, or v av i n = 5v 10%, t a = -40c to +85c. typical are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c parameter symbol test conditions min (note 3) typ max (note 3) unit s 09615 march 14, 2014 rev a
page 7 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation notes: 3. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 4. minimum v in can operate below 5.5v as long as v av i n is greater than 4.5v. 5. maximum v in can be higher than 14v voltage stress across the upper and lower do not exceed 15.5v in all conditions. 6. circuit requires 150ns minimum on time to detect overcurrent condition. 7. limits established by characteri zation and are not production tested. 8. pok rising delay is measured from the point where v out reaches regulation to the point where pok rises. it does not include the external soft-start time. the pok rising delay specification is measured at 500khz. typical performance curves v in = 12v, v out = 2.5v, i o = 2a, f sw = 500khz, l = 4.7h, c in = 20f, c out = 100f + 22f, t a = +25 c, unless otherwise noted . figure 5. efficiency vs load (v in = 5v) figure 6. efficiency vs load (v in = 12v) figure 7. v out regulation vs load (v out = 0.6v, 500khz) figure 8. v out regulation vs load (v out = 1.2v, 500khz) electrical specifications refer to ?block diagram? and ?typical application schematics?. oper ating conditions unless otherwise noted: v in = 12v, or v av i n = 5v 10%, t a = -40c to +85c. typical are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c parameter symbol test conditions min (note 3) typ max (note 3) unit s 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 output load (a) efficiency (%) v out = 2.5v v out = 3.3v v out = 1.8v 40 50 60 70 80 90 100 0.00.51.01.52.02.5 output load (a) efficiency (%) v out = 1.8v v out = 2.5v v out = 5.0v v out = 3.3v 0.6019 0.6020 0.6021 0.6022 0.6023 0.6024 0.6025 0.6026 012 output load (a) output voltage (v) 14v in 9v in 5v in 1.200 1.201 1.202 1.203 1.204 1.205 1.206 012 output load (a) output voltage (v) 9v in 5v in 14v in 09615 march 14, 2014 rev a
page 8 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation figure 9. v out regulation vs load (v out = 1.5v, 500khz) figure 10. v out regulation vs load (v out = 1.8v, 500khz) figure 11. v out regulation vs load (v out = 2.5v, 500khz) figure 12. v out regulation vs load (v out = 3.3v, 500khz) typical performance curves v in = 12v, v out = 2.5v, i o = 2a, f sw = 500khz, l = 4.7h, c in = 20f, c out = 100f + 22f, t a = +25 c, unless otherwise noted . (continued) 1.510 1.512 1.514 1.516 1.518 1.520 012 output load (a) output voltage (v) 5v in 9v in 14v in 1.810 1.811 1.811 1.812 1.812 1.813 1.813 1.814 1.814 1.815 1.815 01 2 output load (a) output voltage (v) 14v in 9v in 5v in 2.505 2.507 2.509 2.511 2.513 2.515 012 output load (a) output voltage (v) 14v in 5v in 9v in 3.345 3.346 3.347 3.348 3.349 3.350 3.351 3.352 3.353 3.354 3.355 012 output load (a) output voltage (v) 9v in 14v in 5v in 09615 march 14, 2014 rev a
page 9 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation figure 13. v out regulation vs load (v out = 5v, 500khz) figure 14. power dissipation vs load (v out = 0.6v, 500khz) figure 15. power dissipation vs load (v out = 1.2v, 500khz) figure 16. power dissipation vs load (v out = 1.5v, 500khz) typical performance curves v in = 12v, v out = 2.5v, i o = 2a, f sw = 500khz, l = 4.7h, c in = 20f, c out = 100f + 22f, t a = +25 c, unless otherwise noted . (continued) 5.020 5.022 5.024 5.026 5.028 5.030 output load (a) output voltage (v) 012 7v in 14v in 9v in 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 012 output load (a) power dissipation (w) 5v in 9v in 14v in 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) power dissipation (w) 012 5v in 9v in 14v in 0.0 0.5 1.0 1.5 2.0 2.5 01 2 output load (a) power dissipation (w) 14v in 9v in 5v in 09615 march 14, 2014 rev a
page 10 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation figure 17. power dissipation vs load (v out = 1.8v, 500khz) figure 18. power dissipation vs load (vout = 2.5v, 500khz) figure 19. power dissipation vs load (v out = 3.3v, 500khz) figure 20. power dissipation vs load (v out = 5v, 500khz) figure 21. v av i n load regulation figure 22. v av i n regulation vs v in typical performance curves v in = 12v, v out = 2.5v, i o = 2a, f sw = 500khz, l = 4.7h, c in = 20f, c out = 100f + 22f, t a = +25 c, unless otherwise noted . (continued) 0.0 0.5 1.0 1.5 2.0 2.5 012 output load (a) power dissipation (w) 14v in 9v in 5v in 0.0 0.5 1.0 1.5 2.0 2.5 01 2 output load (a) power dissipation (w) 14v in 9v in 5v in 0.0 0.5 1.0 1.5 2.0 2.5 01 2 output load (a) power dissipation (w) 5v in 9v in 14v in 0.0 0.5 1.0 1.5 2.0 2.5 01 2 output load (a) power dissipation (w) 9v in 7v in 14v in 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 0 50 100 150 200 250 300 i avin (ma) vcc (v) avin (v) 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 3 5 7 9 10 11 12 13 14 15 v in (v) avin (v) 468 100ma load no load 09615 march 14, 2014 rev a
page 11 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation figure 23. master to slave operation figure 24. master operation at no load figure 25. master operation with full load figure 26. master operation with negative load typical performance curves v in = 12v, v out = 2.5v, i o = 2a, f sw = 500khz, l = 4.7h, c in = 20f, c out = 100f + 22f, t a = +25 c, unless otherwise noted . (continued) v out1 ripple 20mv/div v out2 ripple 20mv/div 0.5s 5v sw1 5v/div sw2 5v/div sw1 5v/div v out1 ripple 20mv/div sync1 2v/div il1 0.5a/div sw1 5v/div vout1 ripple il1 1a/div sync1 5v/div 20mv/div sw1 10v/div vout1 ripple 20mv/div il1 1a/div sync1 5v/div 09615 march 14, 2014 rev a
page 12 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation figure 27. soft-start at no load figure 28. start-up with pre-biased figure 29. soft-start at full load figure 30. positive output short circuit typical performance curves v in = 12v, v out = 2.5v, i o = 2a, f sw = 500khz, l = 4.7h, c in = 20f, c out = 100f + 22f, t a = +25 c, unless otherwise noted . (continued) en1 5v/div v out1 1v/div il1 2a/div ss1 2v/div en1 5v/div vout1 0.5v/div il1 1a/div ss1 2v/div 2v pre-biased en1 5v/div vout1 1v/div il1 1a/div ss1 2v/div sw1 10v/div v out1 1v/div il1 1a/div pok1 5v/div 09615 march 14, 2014 rev a
page 13 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation functional pin descriptions pok (pin 1) pok is an open drain output that pulls to low if the output goes out of regulation or a fault is detected. pok is equipped with a fixed delay upon output power-up. the pok rising delay specificati on is measured at 500 khz from the point where v out reaches regulation to the point where pok rises. this delay is reversely proportional to the switching frequency. agnd (pin 2) the agnd terminal of the ER2120QI provides the return pa th for the control and monitor portions of the ic. en (pin 3) the enable pin is a bi-directional pin. if the voltage on this pin exceeds the enable threshold voltage, the part is enabled. i f a fault is detected, the en pin is pulled lo w via internal circuitry for a duration of four soft-start periods. fo r automatic start-up, us e 10k ? to 100k ? pull-up resistor c onnecting to avin. figure 31. positive output short circuit (hiccup mode) figure 32. negative output short circuit figure 33. recover from positive short circuit figure 34. load transient typical performance curves v in = 12v, v out = 2.5v, i o = 2a, f sw = 500khz, l = 4.7h, c in = 20f, c out = 100f + 22f, t a = +25 c, unless otherwise noted . (continued) sw1 10v/div ss1 2v/div il1 2a/div v out1 2v/div sw1 10v/div pok1 5v/div il1 2a/div v out1 2v/div sw1 10v/div vout1 1v/div il1 1a/div pok1 5v/div sw1 5v/div iout1 2a/div il1 2a/div vout1 ripple 50mv/div 09615 march 14, 2014 rev a
page 14 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation sync (pin 4) sync is a bi-directional pin used to synchr onize slave devices to the master device. as a master device, th is pin outputs the c lock signal to which the slave devices synchronize . as a slave device, this pin is an input to receive the clock signal from the mas ter device. if configured as a slave device, the er2120q i is disabled if there is no clock signal from the master device on the sync pin. leave this pin unconnected if the ic is used in stand-alone operation. m/s (pin 5) as a slave device, tie a 5k ? resistor between the m/s pin and ground. as a master or a stand-alone device, tie the m/s pin dire ctly to the avin pin. do not short the m/s pin to gnd. fsw (pin 6) the fsw pin provides oscillator switching frequency adjustment . by placing a resistor (r t ) from the fsw pin to gnd, the switching frequency can be program med as desired between 500khz and 1.2mhz as shown in equation 1. tying the fsw pin to the avin pin fo rces the switching frequency to 800khz. using resistors with values below 40k ? (1.2mhz) or with values higher than 97k ? (500khz) may damage the ER2120QI. comp (pin 7) and fb (pin 8) the switching regulator employs a single voltage control loop. the fb pin is the negative input to the voltage loop error ampli fier. the output voltage is set by an external re sistor divider connect ed to fb. with a properly sele cted divider, the output voltage can be set to any voltage between th e power rail (reduced by converter losses) and th e 0.6v reference. loop compensation is achieve d by connecting an ac network across the comp pin and the fb pin. the fb pin is also mon itored for undervoltage events. ss (pin 9) connect a capacitor from the ss pin to groun d. this capacitor, along with an internal 30a current source, sets the soft-start interval of the converter, t ss , as shown in equation 2. pgnd (pins 10-13) the pgnd pins are used as the gr ound connection of the power train. sw (pins 14-17) the sw pins are the sw node conne ctions to the inductor. these pins are connected to the source of the control mosfet and the drain of the synchronous mosfet. pvin (pins 18-21) connect the input rail to the pvin pins. these pins are the input to the regulator as well as the source for the internal linea r regulator that supplies the bias for the ic. it is recommended that the dc voltage applied to the pvin pins does not exceed 14v. this reco mmendation allows for transient spikes and voltage ringing to occur while not exceeding absolute maximum ratings. boot (pin 22) the boot pin provides ground-referenced bi as voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage suitable to drive the internal n-channel mo sfet. the boot diode is included within the ER2120QI. r t k ? ?? 48000 f osc khz ?? ------------------------------ = (eq. 1) c ss ? f ?? 50 t ss s ?? ? = (eq. 2) 09615 march 14, 2014 rev a
page 15 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation avino (pin 23) the avino pin is the output of the internal linear regulator that supplies the bias and gate voltage for the ic. a minimum 4.7 f decoupling capacito r is recommended. avin (pin 24) the avin pin supplies the bias voltage for the ic. this pin should be tied to the avino pin through an rc low pass filter. a 10 ? resistor and 0.1f capa citor are recommended. 09615 march 14, 2014 rev a
page 16 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation block diagram gate drive and adaptive shoot thru protection pok ss fb boot sw (x4) oc monitor sync m/s agnd en fsw comp avino clock and oscillator generator pvin series regulator 0.6v reference avino voltage monitor pvin (x4) avino pgnd (x4) oc monitor 30 ? a avin bias fault monitoring por monitor 09615 march 14, 2014 rev a
page 17 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation functional description initialization the ER2120QI automatically initializes upon receipt of input power. the power-on re set (por) function c ontinuously monitors the voltage on the avin pin. if the voltage on the en pin exceeds its rising threshold, then the por function initiates soft-st art operation after the bias voltage has exceeded the por threshold. stand-alone operation the ER2120QI can be configured to function as a stand-al one single channel vol tage mode synchronous buck pwm voltage regulator. the ?typical application sc hematics? on page 3 show the two conf igurations for stand-alone operation. the internal series linear regul ator requires at least 5.5v to create the proper bias for the ic . if the input voltage is betwe en 5.5v and 15v, simply connect the pvin pins to the input rail, and the series linear regula tor creates the bias for the ic. the avin pin should be tied to a ca pacitor for decoupling. if the input voltage is 5v ? 10%, then tie the pvin pins and the avin pin to th e input rail. the ER2120QI us es the 5v rail as the bias. a decoupling capacitor s hould be placed as close as possible to the avin pin. multi-channel (master/slave) operation the ER2120QI can be configured to func tion in a multi-channel system. ?ER2120QI wi th multiple slaved channels? on page 4 shows a typical configuration for the multi-channel system. in the multi-channel system, each ER2120QI ic regulates a separate rail while sharing the same input rail. by configuring the devices in a master/slave c onfiguration, the clocks of each ic can be synchronized. there can only be one master ic in a multi-channel system. to conf igure an ic as the master, the m/s pin must be shorted to the avin pin. the sync pins of all the ER2120QI controller ics in the multi-channel system must be tied together. the frequency set resistor value (r t ) used on the master device must be used on ever y slave device. each slav e device must have a 5k ?? resistor connecting it from m/s pin to ground. the master device and all slave de vices can have their en pins tied to an enable ?bus.? since the en pin is bi-directional, it allows for options on how each ic is tied to the enable bus. if the en pin of any ER2120QI is tie d directly to the enable bus, then that d evice is capable of disabling all the othe r devices that have their en pi ns tied directly to the enable bus. if the en pin of an er2120q i is tied to the enable bus through a diode (anode tied to ER2120QI en pin, ca thode tied to enable bus), then the part does not disable othe r devices on the enable bus if it disables itself for any reason. if the master device is disabled via the en pin, it continues to send the clock signal from the sync pin. this allows slave dev ices to continue operating. fault protection the ER2120QI monitors the output of the regulator for overcurrent and undervoltage events. the ER2120QI also provides protectio n from excessive junction temperatures. overcurrent protection the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through both the upper and lower mosfets. upon detection of any overcurrent condition, the upper mosfet is immediately turned of f and is not turned on again until the next switching cycle. upon detection of the initi al overcurrent condition, th e overcurrent fault counter is set to 1, and the overcurrent condition flag is set from low to high. if, on the s ubsequent cycle, anot her overcurrent condition is detected, the oc fault counter is incremented. if there are eight sequential oc faul t detections, the regulator is shut down under an overcur rent fault condition, and the en pin is pulled low. an overcurrent fa ult condition results, with the regulator attempting to restart in hiccup mode. the delay betwee n restarts is four soft-start periods. at the end of the fourth soft-start wait period, the fault counters are reset, the en pin is released, and soft-start is attemp ted again. if the overcu rrent condition goes away prior to the oc fa ult counter reaching a count of four, the overcu rrent condition flag is set back to low. if the overcurrent condition flag is high, th e overcurrent fault counter is less than four, and an undervoltage event is detect ed, the regulator shut s down immediately. 09615 march 14, 2014 rev a
page 18 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation undervoltage protection if the voltage detected on the fb pin falls 18% below the internal reference voltage, and if the overcurrent condition flag is low, then the regulator is shut down immedi ately under an undervoltage fault conditi on, and the en pin is pulled low. an undervoltage fault condition results in the regulator attempting to restart in hiccup mode, with the de lay between restarts bei ng four soft-start periods. at the end of the fourth soft-start wait period, the fault counters are reset, the en pin is released, and soft- start is attempted again. thermal protection if the ER2120QI ic junction temperature reac hes a nominal temperature of +150c, th e regulator is disabled. the ER2120QI does not re-enable the regulator until the junction temperature drops below +130c. shoot-through protection a shoot-through condition occurs when both the upper and lower mosfets are turned on simultaneously, effectively shorting the input voltage to ground. to protect from a shoot-through conditi on, the ER2120QI incorporates sp ecialized circuitry, which ensures that the complementary mo sfets are not on simultaneously. application guidelines operating frequency the ER2120QI can operate at switching frequenc ies from 500khz to 1.2mhz. a resistor tied from the fsw pin to ground is used to program the switching frequency (equation 3). output voltage selection the output voltage of the regulator can be programmed via an external re sistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier (see figure 36). the output voltage programming resistor, r 4 , depends on the value chosen for the feedback resistor and the de sired output voltage of the regulator. the value for the fee dback resistor is typically between 1k ? and 10k ? . if the output voltage desired is 0.6v, then r 4 is left unpopulated. output capacitor selection an output capacitor is required to filter the inductor current and supply the load transient current. the filtering requirement s are a function of the switching frequency and the ripple current. the load tran sient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are ge nerally met with a mix of ca pacitors and careful layout. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk f ilter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual cap acitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of th e load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these lo w inductance components. consult with the manufacturer of the load on sp ecific decoupli ng requirements. the shape of the output voltage waveform du ring a load transient that represents the worst-case loading conditions ultimately d etermines the number of output capacitors and their t ype. when this load transient is applied to the converter, most of the energy requir ed by the load is initially delivered from the output capacitors. this is due to the finite amount of time re quired for the inductor curr ent to slew up to the level of the output current required by the load. this phenomenon results in a te mporary dip in the output voltage. at the very edge of the transient, the equivalent series induc tance (esl) of each capacito r induces a spike that adds on top of the existing voltag e drop due to the equivalent series resistance (esr). r t k ? ?? 48000 f osc khz ?? ------------------------------ = (eq. 3) r 4 r 1 0.6v ? v out 0.6v ? ---------------------------------- = (eq. 4) 09615 march 14, 2014 rev a
page 19 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation after the initial spike, attributable to the esr and esl of the capacitors, the output voltage experiences sa g. this sag is a d irect consequence of the amount of capacitance on the output. during removal of the same output load, the energy stored in th e inductor is dumped into the output capacitors. this energy dum ping creates a temporary hump in the out put voltage. this hump, as with the sag, can be attributed to the total amount of capacitanc e on the output. figure 35 shows a typical response to a load transient. the amplitudes of the different t ypes of voltage excursions can be approximated using equation 5. where: i tran = output load current transient, and c out = total output capacitance. in a typical converter design, the esr of the output capacitor bank dominates the transient re sponse. the esr and esl typically are the major contributing factors in determining the output capacitance. the number of output capacitors can be determined by using equation 6, which relates the esr a nd esl of the capacitors to the transient load step and the voltage limit (dvo): if dv sag or dv hump is found to be too large for the output voltage lim its, then the amount of capa citance may need to be increased. in this situation, a trade-off between out put inductance and output ca pacitance may be necessary. the esl of the capacitors, which is an important parameter in the previous equa tions, is not usually listed in databooks. practically, it can be a pproximated using equation 7 if an impedance vs frequency curve is given for a specific capacitor: where f res is the frequency at which the lowest impedance is achi eved (resonant frequency). the esl of the capacitors become s a concern when designing circuits that supply pow er to loads with high rates of change in the current. figure 35. typical transient response v out i out dv esl dv esr dv sag dv hump i tran ? v esr esr i tran ? = ? v esl esl di tran dt --------------- ? = ? v sag l out i tran 2 ? c out v in v out ? ?? ? ------------------------------------------------- - = ? v hump l out i tran 2 ? c out v out ? -------------------------------- = (eq. 5) number of capacitors esl d i tran ? dt --------------------------------- esr i tran ? + ? v o ----------------------------------------------------------------------- = (eq. 6) esl 1 c2 ?? f res ? ?? 2 ---------------------------------------- = (eq. 7) 09615 march 14, 2014 rev a
page 20 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation output inductor selection the output inductor is selected to meet the output voltage ripple requirements and to minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current, and the ripple vol tage is a function of the rippl e current. the ripple voltage and current are approximated by using equation 8: increasing the value of inductance reduce s the ripple current and voltage. however, the large inductance values reduce the converter response time to a load transient. one of the parameters limiting conve rter response to a load transient is the time required to change the inductor current. give n a sufficiently fast control loop design, the ER2120QI provides either 0% or 100% duty cycle in response to a load transient. th e response time is the time required to slew the inductor current from an initial current value to the transient current level. d uring this interval, the difference between the inductor current and the tr ansient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is differ ent for the application of load and the re moval of load. equation 9 gives the approxi mate response time interval fo r application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to th e application of load, and t fall is the response time to the removal of load. the worst-case response time can be either at the application or removal of lo ad. be sure to check both of these equations at the minimum and maximum out put levels for the wors t-case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overs hoot across the mosfets. use sm all ceramic capa citors for high - frequency decoupling, a nd bulk capacitors to supply the current needed ea ch time the upper mosfet turns on. place the small ceramic capacitors phys ically close to the mosfets and between the drain of the upper mosfet and the source of the lower mosfet. the important parameters for bul k input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors wi th voltage and current ratings above the maximum i nput voltage and largest rm s current required by the circuit. their voltage rating s hould be at least 1.25x gr eater than the maximum input voltage , while a voltage rating of 1.5x i s a conservative guideline. for most cases, the rms current rating requirement fo r the input capacitor of a buck regulator is approximately one-half the dc load current. the maximum rms current through the input capacitors can be closely approxi mated using equation 10: for a through-hole design, several electrolytic capacitors may be needed. for surface mount desi gns, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge current at power-up. some capacitor series available from reputable manufacturers are surge current tested. feedback compensation figure 36 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (v out ) is regulated to the refere nce voltage level. the error amplifier output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated (pwm ) wave with an amplitude of v pvin at the sw node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is th e small-signal transfer function of v out /v e/a . this function is domin ated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v pvin ) divided by the peak-to-peak oscillator voltage, dv osc . the ER2120QI incorporates a feed-forward l oop that accounts for ch anges in the input voltage. this configuration mainta ins a constant modulator gain. di = vin - vout f sw x l vout vin dvout = di x esr x (eq. 8) t rise = l x i tran vin - vout t fall = l x i tran vout (eq. 9) v out v pvin --------------- - i out max 2 1 v out v pvin -------------- - ? ?? ?? ?? ? 1 12 ------ v in v out ? lf osc ? ----------------------------- v out v pvin --------------- - ? ?? ?? ?? 2 ? + ?? ?? ?? ? (eq. 10) 09615 march 14, 2014 rev a
page 21 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation modulator break frequency equations the compensation network consists of the error amplifier (internal to the ER2120QI) and the impe dance networks, z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 degrees. equation 12 relates the compensation network?s poles, zeros, and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 and c 3 ) in figure 36. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r 2 /r 1 ) for desired converter bandwidth. 2. place first zero below fi lter?s double pole (~75% f lc ). 3. place second zero at filter?s double pole. 4. place first pole at esr zero. 5. place second pole at half the switching frequency. 6. check gain against error amplifier?s open-loop gain. 7. estimate phase margin; repeat if necessary. figure 36. voltage-mode buck converter compensation design and output voltage selection v out reference l o c o esr v in ? v osc error amp pwm driver (parasitic) z fb + - reference r 1 r 3 r 2 c 3 c 1 c 2 comp v out fb z fb z in comparator driver detailed compensation components sw v e/a + - + - z in osc r 4 v out 0.6 1 r 1 r 4 ------ -+ ?? ?? ?? ? ? ? 09615 march 14, 2014 rev a
page 22 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation compensation break frequency equations figure 37 shows an asymptotic plot of the dc/dc converter gain vs frequency. the actu al modulator gain has a high gain peak due to the high q factor of the output filter and is not shown in figure 37. using the guidelines provided should give a compensati on gain similar to the curve plotted. the open loop error amplifier gain bounds the co mpensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is construc ted on the graph of figure 37 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to t he compensation transfer function and plotting the gain. the compensation gain uses ex ternal impedanc e networks, z fb and z in , to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing wi th -20db/decade slope and a phase margin greater than +45. include worst-case component variations when determining phase margin. layout considerations layout is very important in hi gh frequency switching converter design. with pow er devices switching ef ficiently between 500khz and 1.2mhz, the resulting current transitions from one device to another cause voltage spik es across the interconnecting impedances and parasitic ci rcuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit, and lea d to device overvoltage stre ss. careful component layout a nd printed circuit board design mi nimize these voltage spikes. as an example, consider the turn-off transition of the control mosfet. prior to turn-off, the mo sfet is carrying the full load current. during turn-off, current stops flow ing in the mosfet and is picked up by th e lower mosfet. any parasitic inductance in the switched current path generates a large voltage spike during the switching inte rval. careful component selection, tight layout of the critical components, and short, wide traces minimize the magnitude of voltage spikes. there are two sets of critical component s in the ER2120QI switching converter. the switching components are the most critical because they switch large amounts of en ergy and therefore tend to generate large amounts of noise. next are the small signal components, which connect to sensitive nodes or su pply critical bypass cu rrent and signal coupling. a multi-layer printed circuit board is reco mmended. figure 38 shows th e connections of the critica l components in the converter . note that capacitors c in and c out could each represent numerous p hysical capacitors. de dicate one solid laye r (usually a middle layer of the pc board) for a ground plane, a nd make all critical component ground connectio ns with vias to th is layer. dedicate another solid layer as a power plane, and br eak this plane into smaller islands of co mmon voltage levels. ke ep the metal runs f rom the sw terminals to the output inductor short. the power pl ane should support the input pow er and output power nodes. use copper-filled polygons on the top and bottom ci rcuit layers for the phase nodes. use the remaining pr inted circuit layers for s mall signal wiring. the wiring traces from the ga te pins to the mosfet gate s should be kept short and wide enough to easily handle the 1a of drive current. f z1 1 2 ? x r 2 x c 1 ------------------------------------ = f z2 1 2 ? x r 1 r 3 + ?? x c 3 ------------------------------------------------------ - = f p1 1 2 ? x r 2 x c 1 x c 2 c 1 c 2 + --------------------- - ?? ?? ?? -------------------------------------------------------- - = f p2 1 2 ? x r 3 x c 3 ------------------------------------ = (eq. 12) 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 20log f lc f esr compensation gain (db) frequency (hz) gain 20log (v in / ? v osc ) modulator gain (r 2 /r 1 ) closed loop gain figure 37. asymptotic bode plot of converter gain 09615 march 14, 2014 rev a
page 23 ER2120QI 2a synchronous buck regulator with integrated mosfets march 2014 altera corporation in order to dissipate heat generated by the internal v tt ldo, the ground pad, pin 29, should be connected to the internal ground plane through at least five vias . this allows heat to move away from the ic and also ties the pad to the ground plane through a low impedance path. the switching components should be placed close to the ER2120QI fi rst. minimize the length of connections between the input capacitors, c in , and the power switches by placing them nearby. position bot h the ceramic and bulk input ca pacitors as close to the upper mosfet drain as possible. position the output inductor and output capacitors between the upper and lower mosfets and the load. make the pgnd and the output capacitors as short as possible. the critical small signal components incl ude any bypass capacitors, fe edback components, and comp ensation components. place the pwm converter compensation components close to the fb and co mp pins. the feedback resistor s should be located as close as possible to the fb pin, with vias tied straight to the ground plane as required. document revision history the table lists the revision history for this document. figure 38. printed circuit board power planes and islands date version changes march 2014 1.0 initial release. pvin avino avin sw pgnd comp fb gnd pad r 4 r 3 c 3 r 1 c 1 c 2 r 2 c out1 v out1 c in v in l 1 c bp2 r bp c bp1 5v island on power plane layer island on circuit and/or power plane layer via connection to ground plane key load ER2120QI 09615 march 14, 2014 rev a
page 24 ER2120QI 2a synchronous buck regulator with in tegrated mosfets march 2014 altera corporation package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 09615 march 14, 2014 rev a

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